In the recent development of CMOS (complementary MOS) devices for which smaller and smaller transistors are required, the deterioration of the driving current due to the depletion of gate electrodes is posing a problem. In view of this problem, a so-called metal gate technique by which metallic materials are used in place of the traditional polycrystalline silicon is being studied with a view to enhancing the driving capacity.
On the other hand, along with miniaturization of transistors an increase in the gate leak current due to the thinning of the gate insulating film is posing a problem. For this reason, a reduction in the gate leak current by increasing the physical film thickness by using a high dielectric constant material (high-k material) for the gate insulating film is being studied with a view to reducing the power consumption.
As the material for use in the metal gate electrode, pure metal, metal nitride or silicide material is considered, but in any case the material is required (1) that formation of the metal gate electrode should not give rise to deterioration of the gate insulating film and (2) the threshold voltages (Vth) of the N-type MOSFET and of the P-type MOSFET should permit setting to appropriate values.
In order to realize a Vth level of not more than ±0.5 eV for CMOS transistors, it is necessary to use for a gate electrode material of which the work function is not greater than the mid-gap of Si (4.6 eV), desirably not more than 4.4 eV, for N-type MOSFETs and one of which the work function is not smaller than the mid-gap (4.6 eV) of Si, desirably not less than 4.8 eV, for P-type MOSFETs.
As means of realizing these objectives, a method of controlling the Vth of transistors by separately using metals or alloys having different work functions optimal for the gate electrodes of N-type MOSFETs and P-type MOSFETs to form different gates (dual metal gate technique), is proposed.
For instance, it is stated in Non-Patent Document 1 (International electron devices meeting technical digest 2002, p. 359) that the work functions of Ta and Ru formed over SiO2 are respectively 4.15 eV and 4.95 eV, and work function modulation by 0.8 eV is possible between these two electrodes.
However, since the dual metal gate technique described requires separate preparation of metal layers made up of different metals or alloys having different work functions over a substrate, the metal layer deposited on the gate insulating film of either the P-type MOSFET or the N-type MOSFET has to be etched off and, as this invites deterioration of the quality of the gate insulating film in the etching process, accordingly there is a problem of adversely affecting the characteristics and reliability of elements.
On the other hand, there is proposed a technique regarding a silicide electrode obtained by fully siliciding a polycrystalline silicon electrode pattern with Ni. This technique permits silicidation of the polycrystalline silicon electrode pattern by a salicidation process after high temperature heat treatment to activate impurities in the source/drain region of CMOS. For this reason, it is highly compatible with conventional CMOS processes and, because the film stacked over the gate insulating film need not be removed by etching unlike the dual metal gate technique, damage to the gate insulating film can be suppressed.
In particular Non-Patent Document 2 (International electron devices meeting technical digest 2004, p. 91) discloses that the effective work function can be controlled in a wide range of transistors, in a MOSFET using a HfSiON high dielectric constant film as the gate insulating film and a fully silicided Ni silicide electrode as the gate electrode, by regulating the composition ratio of the Ni silicide by utilizing the formation of a crystalline phase. It is further stated that a Vth of ±0.3 V can be realized by utilizing the formation of an Ni3Si phase, an NiSi phase and an NiSi2 phase.
However, even these techniques still involve the following problems which the dual metal gate technique has. Thus, the dual metal gate technique is susceptible, in a structure in which the gate electrode of the N-type MOSFET and the gate electrode of the P-type MOSFET are made up of one line of electrodes, to the diffusion of the constituent materials on the interface between the two gate electrodes. When this diffusion proceeds to a considerable degree, the composition of materials varies to make impossible to obtain the designed work function and makes the characteristics of operation difficult to control. Although Patent Document 1 (Japanese Patent Application Laid Open No. 2004-221226) describes a method intended to solve this problem, a superior diffusion preventive technique is called for.